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Configuration of VLSI Arrays in the Presence of Defects
Circuit area fault tolerance percolation theory probabilistic analysis queuing processes systolic arrays wafer-scale integration wire length
2015/8/12
The penalties for configuring VLSI arrays for yield enhancement are assessed. Each dement of the fabricated array is assumed to be defective with independent probability p. A fixed fractmn R of the el...
Self-tuning for maximized lifetime energy-efficiency in the presence of circuit aging
Integration framework optimizing control strategy of dynamic control self-tuning parameters circuit aging supply voltage
2015/8/7
This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit a...
A 22% Efficient Semiconductor/Liquid Junction Solar Cell—the Photoelectrochemical Behavior of n-WSe2 Electrodes in the Presence of I2/I- in Aqueous Electrolyte
Aqueous Electrolyte n-WSe2 Electrodes the Photoelectrochemical Behavior Semiconductor/Liquid Junction Solar Cell
2010/12/21
One of the most efficient semiconductor/liquid-junction photoelectrochemical cells (PEC) reported to date is presented. It consists of a SeCl4-grown n-WSe2 single crystal anode, with a 3.1016 cm-3 con...