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A high Speed 8 Transistor Full Adder Design using Novel 3 Transistor XOR Gates
XOR gate full adder improvement in speed area minimization
2010/2/2
The paper proposes the novel design of a 3T XOR
gate combining complementary CMOS with pass transistor logic.
The design has been compared with earlier proposed 4T and 6T XOR
gates and a significan...
Model Order Reduction of Linear Time Variant High Speed VLSI Interconnects using Frequency
Model order Reduction RLC crosstalk
2010/2/2
Accurate modeling of high speed RLC interconnects
has become a necessity to address signal integrity issues in current
VLSI design. To accurately model a dispersive system of interconnects
at highe...
Fast and Efficient On-Chip Interconnection Modeling for High Speed VLSI Systems
IC design RC/RLC Interconnection VLSI Systems
2010/2/2
Timing driven physical design, synthesis, and
optimization tools need efficient closed-form delay models for
estimating the delay associated with each net in an integrated circuit
(IC) design. The ...
Design of High-Speed CMOS Ics for 10 Gbit/s Optical Communication System
Design CMOS Ics Optical Communication System
2010/7/15
In this paper, the intrinsic disadvantages of the nowadays low-cost deep-submicron digital CMOS technologies in respect of the design of high-speed optical communication (OC)
systems front-end integr...