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High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m)
Cryptography Logical Effort Gaussian Normal Basis multiplication
2016/12/8
In this paper, by employing the logical effort technique an efficient and high-speed VLSI implementation of the digit-serial Gaussian normal basis multiplier is presented. It is constructed by using A...
VLSI Implementation of Double-Base Scalar Multiplication on a Twisted Edwards Curve with an Efficiently Computable Endomorphism
Multiple-precision arithmetic Pseudo-Mersenne prime
2015/12/30
The verification of an ECDSA signature requires a double-base scalar multiplication, an operation of the form k⋅G+l⋅Q where G is a generator of a large elliptic curve group of prime order ...
提出了一种简化的抗零值差分功耗分析的先进密码算法(AES)及其VLSI实现方案。为了降低抗攻击技术对原有运算单元速度面积的影响，在分析原改进的AES算法的基础上，提出了更为简单的加法性屏蔽算法，并用复用相应模块、优化运算次序等方法实现了以极小的硬件代价获得很高的抗攻击性能。设计采用HHNEC 0.25µm标准CMOS工艺，单元面积约43k等效门。在40MHz工作频率下，128-bit加...
低复杂度先进密码算法的VLSI实现
AES 低成本 字节替换 复合域
2008/5/15
提出了一种先进密码算法(AES)的低成本VLSI实现方案。从分析AES算法入手，优化运算次序，实现相应模块的复用，从而达到缩小芯片面积的目标，同时将关键的字节替换(SubByte)模块转化到对应的复合域中进行运算，进一步减小芯片复杂度。基于HHNEC 0.25μm标准CMOS工艺，芯片工作频率可以达到100MHz，密钥为128bits时，芯片的加解密速度可达800Mps，而芯片规模不超过 ...